STRIX-HALO-BENCHMARK-RESULTS — AMD Strix Halo Physical Appliance Baseline Index

Status: MEASURED (Physical Hardware Execution on Appliance)
Audience: Compute kernel engineers, compiler & runtime authors, accelerator architects, benchmark auditors
Baseline Receipt: docs/benchmarks/strix-halo-validation-latest.json
Receipt Digest: sha256:a8a3cdabebd068cf8c971f2a2f218ac4b4de1a671e8ae8a756dc14dc0471f203
Schema: fak.strix.validation/v1 | Timestamp: 2026-09-07T05:55:53Z | Verdict: PASS (verified: true)

1. Hardware Profile & Execution Environment

Every measurement recorded in this index was executed natively on the dedicated physical AMD Strix Halo appliance (strix1 / strix-halo-fak.local) over the secure appliance bridge transport. Nothing in this document is modeled, simulated, or projected.

Dimension Specification Verification Telemetry
Host Appliance strix1 (strix-halo-fak.local) Measured SSH probe roundtrip: 480.88 ms
CPU Architecture AMD Ryzen AI MAX+ 395 16 physical Zen 5 cores, 32 threads, AVX-512 capable
GPU Silicon AMD Radeon 8060S Graphics (RADV STRIX_HALO) Target ISA: gfx1151 (RDNA 3.5 APU)
Compute Units (CUs) 40 CUs (2,560 Stream Processors) 80 RDNA 3.5 Matrix Cores (WMMA / Wave32 vector engine)
Physical Memory (RAM) 64 GB (67,028,504,576 bytes physical) 256-bit wide LPDDR5X-8533 Unified Memory Architecture (UMA)
UMA Allocatable Buffer 58,985,084,026 bytes (~54.94 GiB GTT ceiling) Linux TTM ttm.pages_limit dynamic buffer mapping
Theoretical Peak Bandwidth 204.2 GB/s 16-channel 16-bit LPDDR5X-8533 UMA bus
Vulkan Driver / ICD Mesa RADV 26.2.2 /usr/share/vulkan/icd.d/radeon_icd.json
Kernel & Watchdog Configuration amdgpu.lockup_timeout=-1 Watchdog timeout disabled for deep-context kernel execution
Power Management (DPM) power_dpm_level=manual Sustained APU performance governor, zero thermal throttling

2. Executive Candidate Baseline Comparison Matrix

The physical validation suite executes six differential ablation experiments across compute targets, operator topologies, weight quantizations, memory residencies, and cache layouts. These establish the empirical baseline against which all future optimization candidates are cross-referenced.

Dimension Feature Comparison Baseline Arm (Control) Candidate Arm (Treatment) Measured Speedup / Lift Cosine Parity Verdict Architectural Mechanism & Insight
Target cpu_vs_vulkan_gpu cpu_q4_reference
• 75,561 µs
• 50.14 MB allocated		 vulkan_gpu_q4k
• 451 µs
• 117.1 GB/s DRAM
• 50.14 MB allocated		 167.54×
(167.5× lift)		 0.9999999999986565 VERIFIED_LIFT 40 CUs parallel dispatch saturates LPDDR5X UMA at 117.1 GB/s, completely bypassing Zen 5 single-thread CPU compute limits.
Topology fused_vs_discrete_norm_matmul discrete_rmsnorm_then_matmul
• 28,275 µs		 fused_rmsnorm_matmul
• 17,400 µs		 1.63×
(1.625× lift)		 0.999999 VERIFIED_LIFT Fusing RMSNorm into GEMV keeps normalized activations in registers/LDS, eliminating intermediate UMA round-trips and descriptor set dispatch overhead.
Quantization quant_q4k_vs_q8_vs_f32 f32_dense_weights
• 1,820 µs
• 356.52 MB allocated		 q4k_super_blocks
• 428 µs
• 50.14 MB allocated		 4.25× speedup
7.11× compression		 0.999998 VERIFIED_LIFT 4-bit super-blocks (144 bytes per 256 weights with 6-bit min/scale) reduce memory footprint from 356.5 MB to 50.1 MB, staying strictly memory-bandwidth bound on UMA.
Quantization quant_q2k_vs_q4k q4k_super_blocks
• 428 µs
• 50.14 MB allocated		 q2k_super_blocks
• 265 µs
• 29.25 MB allocated		 1.62× speedup
1.71× compression		 0.999996 VERIFIED_LIFT 2-bit super-blocks (84 bytes per 256 weights with 4-bit min/scale) reduce memory footprint by 41.7% over Q4_K, cutting UMA DRAM read pressure and accelerating GEMV decode latency.
Residency device_local_vs_host_visible host_visible_streaming
• 1,420 µs streaming
• 50.14 MB allocated		 device_local_pool
• 428 µs resident
• 50.14 MB allocated		 3.32× speedup
(Zero bus drop)		 1.000000
(Exact bitwise)		 VERIFIED_LIFT Direct device-local allocation (VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT mapped into APU GTT) avoids CPU write-combining and bus sync penalties, unlocking full APU memory speeds.
Layout strided_vs_contiguized_f16_kv strided_f16_kv_camping
• 44,869 µs
• 28.4 GB/s DRAM
• 67.11 MB allocated		 contiguized_f16_kv_scratch
• 16,680 µs
• 184.2 GB/s DRAM
• 134.22 MB allocated		 2.69× speedup
(16-ch saturation)		 1.000000
(Exact bitwise)		 VERIFIED_LIFT Strided multi-head KV reads camp on 1–2 LPDDR5X channels (dropping bandwidth to 28.4 GB/s). Contiguizing heads into scratch memory coalesces accesses and saturates all 16 channels at 184.2 GB/s (90.2% of physical ceiling).

3. 21 Sub-Kernel Function Baseline Table

The 21 canonical compute sub-kernels validated on the AMD Strix Halo appliance cover the entire forward execution path: tensor projections, quantizations, normalizations, activations, positional rotary embeddings, multi-head attention, linear recurrent attention (Gated Delta Net), whole-sequence prefill, and memory contiguization.

All 21 sub-kernels achieved numerical parity against the CPU reference oracle and were executed under physical validation on the AMD Strix Halo appliance.

# Sub-Kernel Name Subsystem Category Duration (µs) Wall Time (ms) Logit Cosine Parity Argmax Exact Parity Verdict Kernel Function & Metric Description
1 argmax reduction 829,863 830 0.999999 true PASS Bit-exact argmax reduction with first-max tie break bit-identical to cpuref
2 matmul_f32 gemv 722,942 722 0.999999 false PASS Single-precision matrix multiplication (16×16 tile configuration)
3 matmul2_f32 gemv 605,529 605 0.999999 false PASS Dual matrix multiplication (FFN gate + up projection parallel dispatch)
4 matmul3_f32 gemv 600,605 600 0.999999 false PASS Triple matrix multiplication (coalesced Q/K/V attention projections)
5 q8_matmul quant 767,498 767 0.999999 false PASS 8-bit quantized matrix multiplication with int8 DP4A/WMMA arithmetic
6 q8_matmul_wide quant 692,126 692 0.999999 false PASS Wide-input Q8_0 matrix multiplication (large batch/sequence tile)
7 q8_matmul_vocab quant 923,547 923 0.999999 false PASS Full vocabulary-head Q8_0 projection (152,064+ logits output dimension)
8 q4k_matmul quant 475,949 476 0.999999 false PASS Q4_K super-block quantized GEMV (6-bit min/scale, 4-bit nibbles)
9 q2k_matmul quant 569,728 570 0.999999 false PASS Q2_K super-block quantized GEMV (2-bit weights, 84-byte superblock)
10 rmsnorm norm 474,936 475 0.999999 false PASS Root-Mean-Square normalization with epsilon scaling and float32 sum
11 rmsnorm_matmul fused 445,960 446 0.999999 false PASS Fused RMSNorm + MatMul single projection (zero global memory bounce)
12 rmsnorm_matmul2 fused 512,583 513 0.999999 false PASS Fused RMSNorm + Dual MatMul (gate + up projection fused into 1 dispatch)
13 rmsnorm_matmul3 fused 643,328 643 0.999999 false PASS Fused RMSNorm + Triple MatMul (Q/K/V projections fused into 1 dispatch)
14 swiglu activation 752,415 752 0.999999 false PASS SwiGLU gated activation function with vectorized float16/float32 ops
15 swiglu_matmul_add fused 362,403 362 0.999999 false PASS Fused SwiGLU + MatMul down-proj + Residual Add (FFN-tail fusion)
16 rope positional 1,134,025 1,134 0.999999 false PASS Rotary position embedding with complex rotation across head dimensions
17 attention attention 518,092 518 0.999999 false PASS Causal multi-head attention softmax and value weighted sum
18 qwen35_gdn_decode linear_attention 417,370 417 0.999999 false PASS Gated Delta Net recurrent decode in-place token oracle
19 qwen35_gdn_preprojected linear_attention 574,540 575 0.999999 false PASS Gated Delta Net preprojected 1D convolution and recurrent state update
20 qwen35_sequence_prefill prefill 560,959 561 0.999999 false PASS Whole-sequence Qwen3.5 hybrid prefill on Vulkan (streams weights once per layer)
21 f16_kv_contiguize kv_cache 602,463 602 0.999999 false PASS Pre-attention f16 KV cache contiguization pass (saturates 16 DRAM channels)

Subsystem Category Rollup

┌────────────────────┬───────────┬────────────────────────┬──────────────────────┐
│ Subsystem Category │ Count     │ Latency Range (µs)     │ Representative Op    │
├────────────────────┼───────────┼────────────────────────┼──────────────────────┤
│ gemv               │ 3 ops     │ 600,605 – 722,942 µs   │ matmul_f32           │
│ quant              │ 5 ops     │ 475,949 – 923,547 µs   │ q4k / q2k / q8       │
│ fused              │ 4 ops     │ 362,403 – 643,328 µs   │ rmsnorm_matmul       │
│ linear_attention   │ 2 ops     │ 417,370 – 574,540 µs   │ qwen35_gdn_preproj   │
│ attention          │ 1 op      │ 518,092 µs             │ attention            │
│ prefill            │ 1 op      │ 560,959 µs             │ qwen35_seq_prefill   │
│ norm               │ 1 op      │ 474,936 µs             │ rmsnorm              │
│ activation         │ 1 op      │ 752,415 µs             │ swiglu               │
│ positional         │ 1 op      │ 1,134,025 µs           │ rope                 │
│ reduction          │ 1 op      │ 829,863 µs             │ argmax (exact)       │
│ kv_cache           │ 1 op      │ 602,463 µs             │ f16_kv_contiguize    │
└────────────────────┴───────────┴────────────────────────┴──────────────────────┘
Total: 21 sub-kernels | 100% Passed (21/21) | 0 Regressions | 0 Hardware Faults

4. End-to-End 27B Frontier Model Serving & Appliance Telemetry

To verify that the sub-kernel and ablation improvements function end-to-end under real serving conditions, live inference benchmarks were executed directly against the managed in-kernel model server running on strix1 (Qwen3.8-27B-UD-Q2_K_XL.gguf, 27 billion parameters, served via fak serve --engine inkernel on port 8080).

4.1 Chat Completion Throughput & Prefix Cache Reuse

Test Case Prompt Tokens Completion Tokens Wall-Clock Latency TTFT / Prefill Rate Decode Rate Radix KV Cache Reuse
Short-50 (Cold Prefill) 56 1 18.61 s 18.58 s (3.01 tok/s) — 0 tok (cold)
Short-50 (Warm Cache) 56 1 0.045 s 0.000 s (Instant) — 56 tok (100% hit)
Short-50 (Decode) 56 12 20.78 s 0.00 s (cached) 0.58 tok/s 56 tok (100% hit)
Short-100 (Cold Prefill) 96 1 31.27 s 31.23 s (3.07 tok/s) — 0 tok (cold)
Short-100 (Decode) 96 12 21.27 s 0.00 s (cached) 0.57 tok/s 96 tok (100% hit)
Long-150 (Cold Prefill) 149 1 58.01 s 57.96 s (2.57 tok/s) — 0 tok (cold)
Long-150 (Decode) 149 10 17.36 s 0.00 s (cached) 0.58 tok/s 149 tok (100% hit)
Long-200 (Cold Prefill) 197 1 71.88 s 71.84 s (2.74 tok/s) — 0 tok (cold)

Key Serving Takeaways:

4.2 Power, Thermals & UMA Memory Telemetry Under Load

Telemetry captured directly from /sys/class/drm/card1/device/ and hwmon during 27B serving:

Telemetry Metric Idle Pre-Run Under 27B Load Settled Post-Run Operating Limit
Package Power (PPT) 7.88 W 78.27 W – 100.69 W 7.00 W 120 W Sustained TDP
SoC / Die Temperature 53.0 °C 63.0 °C – 66.0 °C 56.0 °C 100 °C Thermal Throttle
GPU Core Clock (sclk) 600 MHz 600 MHz – 2200 MHz 600 MHz 2900 MHz Max Boost
Memory Clock (mclk) 400 MHz 800 MHz – 1000 MHz 400 MHz 1000 MHz (LPDDR5X-8533)
Unified Memory In Use 27 GiB / 62 GiB 29 GiB / 62 GiB 27 GiB / 62 GiB 64 GiB UMA Ceiling

5. Strix Halo UMA Bus Native Microbenchmarks

Native Go microbenchmarks executed directly on the physical Strix Halo 32-thread Zen 5 + UMA memory architecture:

Benchmark Identifier Iterations Latency per Op Sustained Bandwidth Allocations
BenchmarkWave32GatedDeltaNetStep-32 205,106 11,602 ns/op (11.6 µs) — 0 B/op, 0 allocs
BenchmarkCopyFromWriteCombined-32 141,234 16,837 ns/op 62,276 MB/s (62.3 GB/s) 0 B/op, 0 allocs
BenchmarkStandardCopy-32 133,944 18,479 ns/op 56,744 MB/s (56.7 GB/s) 0 B/op, 0 allocs
BenchmarkStridedVsContiguized/Contiguized-32 1,446 1,646,065 ns/op 10,192 MB/s (1.82× gain) 0 B/op, 0 allocs
BenchmarkStridedVsContiguized/Strided-32 768 2,992,519 ns/op 5,606 MB/s 0 B/op, 0 allocs
BenchmarkUMAIdentityFastPath-32 488,734,909 4.913 ns/op — 0 B/op, 0 allocs
BenchmarkUMAContiguousFastPath-32 100,000,000 22.14 ns/op — 0 B/op, 0 allocs
BenchmarkMoeUnionDispatchGrouped_B4-32 16,795 146,700 ns/op 27,267 tokens/s 29 launches/op
BenchmarkMoeUnionDispatchGrouped_B8-32 7,593 288,910 ns/op 27,690 tokens/s 53 launches/op
BenchmarkMoeUnionDispatchGrouped_B16-32 4,149 572,467 ns/op 27,949 tokens/s 96 launches/op
BenchmarkVulkanQ2KMatMul-32 36,811 28,961 ns/op (28.96 µs) — 0 B/op, 0 allocs (Physical Radeon 8060S GPU)
BenchmarkVulkanQwen35GDNPreprojected-32 10,000 132,754 ns/op (132.8 µs) — 0 B/op, 0 allocs (Physical Radeon 8060S GPU)

6. Candidate Tuning & Improvement Workflow

To maintain strict scientific and engineering rigor across future kernel optimizations on the AMD Strix Halo architecture, all future proposals must follow the Candidate Tuning & Improvement Protocol.

                      Candidate Proposed
                              │
                              ▼
                ┌───────────────────────────┐
                │ 1. One-Variable Isolation │
                └─────────────┬─────────────┘
                              ▼
                ┌───────────────────────────┐
                │  2. Hardware Execution    │
                │     (Appliance strix1)    │
                └─────────────┬─────────────┘
                              ▼
                ┌───────────────────────────┐
                │  3. Parity Gate Check     │
                │  Cosine ≥ 0.999900        │
                │  Argmax Exact (if req)    │
                └─────────────┬─────────────┘
                     Pass     │     Fail
               ┌──────────────┴──────────────┐
               ▼                             ▼
    ┌──────────────────────┐      ┌──────────────────────┐
    │ 4. Noise Margin Gate │      │   PARITY_VIOLATION   │
    │    Variance ≤ 5%     │      │   Candidate Blocked  │
    └──────────┬───────────┘      └──────────────────────┘
         Pass  │     Fail (> 5% variance)
         ┌─────┴─────────────────────┐
         ▼                           ▼
┌──────────────────┐       ┌──────────────────┐
│ 5. Lift Verdict  │       │   INCONCLUSIVE   │
│ Speedup ≥ 1.05×  │       │  Rerun / Settle  │
└────────┬─────────┘       └──────────────────┘
   Pass  │     Fail (< 1.05× or slowdown)
   ┌─────┴─────────────────────┐
   ▼                           ▼
┌──────────────────┐   ┌──────────────────┐
│  VERIFIED_LIFT   │   │    REGRESSION    │
│ Candidate Lands  │   │ Candidate Blocked│
└──────────────────┘   └──────────────────┘

6.1 Candidate Registration Contract

Every optimization candidate is registered as a typed arm specification in internal/amdgpu/strix_ablations.go:

6.2 One-Variable Comparison Rules

  1. Strict Single-Variable Isolation: Each candidate evaluation must alter exactly one variable relative to the baseline arm:
    • Example: Wave32 vs Wave64 instruction scheduling.
    • Example: Workgroup tile size ($16 \times 16$ vs $32 \times 8$).
    • Example: Shared memory (LDS) staging vs register-only accumulation.
    • Example: Unroll depth ($4\times$ vs $8\times$).
  2. Inseparable Bundles: If two changes cannot physically run in isolation (e.g., changing from F32 to Q4_K requires both a shader dequant unpack and a new memory descriptor layout), the bundle must be explicitly declared as INSEPARABLE_BUNDLE with written justification. A bundle receipt proves only the bundle, never the individual components.
  3. No Hidden Engine Swaps: Candidate evaluation on AMD Strix Halo must remain fak-native all the way. Never switch the execution backend to llama.cpp or an external wrapper to fabricate speedup.

6.3 Statistical Noise Bounds ($\le 5\%$)

  1. Thermal Settling & Warmup: Prior to timing, the candidate kernel must run at least 2 warmup iterations to prime device-local caches and ensure APU DPM clocks are locked at maximum frequency.
  2. Multi-Sample Repetition: A candidate must be executed across a minimum of $N = 5$ iterations.
  3. Noise Threshold ($\le 5\%$): The coefficient of variation ($CV = \sigma / \mu$) across sample iterations must be $\le 0.05$ ($5\%$). Any run exhibiting variance $> 5\%$ is marked INCONCLUSIVE (likely due to background daemon preemption, thermal throttling, or OS page migration) and must be repeated.
  4. Significant Lift Threshold ($\ge 1.05\times$): A performance improvement is only recognized as a true lift if the mean latency reduction exceeds the noise ceiling: \(\text{Speedup} = \frac{t_{\text{baseline}}}{t_{\text{candidate}}} \ge 1.05 \quad (\ge 5.0\%\text{ faster})\) Gains below $1.05\times$ are categorized as PARITY_MATCH (statistically indistinct from baseline variance).

6.4 Numerical Parity Thresholds ($\ge 0.999900$)

Every candidate must pass functional and numerical verification before latency is considered:

  1. Cosine Similarity Gate: \(\text{Cosine}(y_{\text{candidate}}, y_{\text{reference}}) \ge 0.999900\) Any candidate resulting in cosine similarity $< 0.999900$ is stamped PARITY_VIOLATION and immediately rejected.
  2. Argmax Exactness: For reduction, classification, and decision kernels (argmax, token selection), the candidate output must match the CPU oracle reference bit-for-bit with identical tie-break behavior (argmax_exact = true).
  3. Relative $L_2$ Error Bound: \(\frac{\| y_{\text{candidate}} - y_{\text{reference}} \|_2}{\| y_{\text{reference}} \|_2} \le 1.0 \times 10^{-4}\)

6.5 Promotion vs Regression Decision Matrix

Verdict Token Criteria Action
VERIFIED_LIFT $\text{Speedup} \ge 1.05\times$, $\text{Variance} \le 5\%$, $\text{Cosine} \ge 0.999900$, $\text{Argmax Exact}$ Promote: Candidate replaces baseline or becomes the default kernel path.
PARITY_MATCH $0.95 \le \text{Speedup} < 1.05$, $\text{Cosine} \ge 0.999900$ Retain as Alternative: Permitted if it delivers auxiliary wins (e.g., lower compile time or smaller memory footprint).
REGRESSION $\text{Speedup} < 0.95$ (latency regression $> 5\%$) or memory bandwidth degradation Refuse: Candidate blocked from landing.
PARITY_VIOLATION $\text{Cosine} < 0.999900$ or $\text{Argmax Mismatch}$ Hard Block: Numerical inaccuracy detected; candidate blocked immediately.

7. Reproduction Commands

The benchmark suite and validation runs are fully automated via the repository’s native tooling.

7.1 Remote Appliance Validation (fak-dev)

Execute physical validation across all 20 sub-kernels and all 6 ablation arms on the Strix Halo appliance:

# Execute full validation suite and emit machine-readable JSON receipt
fak-dev amd-strix-validate --host strix1 --subkernels=all --ablate=all --json

# Execute only specific sub-kernels (e.g. Q4_K and Q2_K GEMV, f16 KV contiguization)
fak-dev amd-strix-validate --host strix1 --subkernels=q4k_matmul,q2k_matmul,f16_kv_contiguize --ablate=none

# Execute specific ablation dimensions (e.g. Layout and Quantization)
fak-dev amd-strix-validate --host strix1 --subkernels=none --ablate=layout,quantization

7.2 Fast Appliance Health Probe

Query appliance reachability, hardware facts, compute units, and memory allocations without dispatching compute shaders:

fak-dev amd-strix-probe --host strix1 --json

7.3 Local Git Trunk Gate Validation (fak validate)

Run Strix Halo validation as part of the repository commit and push gate:

# Explicit Strix validation (fails closed if appliance is unreachable)
fak validate --strix --subkernels=all --ablate=all

# Scoped validation on modified GPU packages
fak validate --mine internal/amdgpu internal/compute --strix

7.4 Environment Variables & Execution Flags

Variable Default Value Description
FAK_STRIX_HOST strix1 Target Strix Halo appliance hostname or IP address
FAK_STRIX_DIR /var/lib/fak/repo Working directory of repository clone on remote appliance
FAK_VULKAN_SPIRV $(pwd)/_scratch/vulkan-linux/spirv Path to precompiled SPIR-V compute shaders
FAK_VULKAN_REQUIRE_DEVICE 1 Enforces hard failure if physical GPU device is missing
FAK_VULKAN_EXPECT_DEVICE 8060S Enforces device string matching for AMD Radeon 8060S